Citrini Analyst: Rubin Ultra HBM Stacking Layer Reduction May Expand Total Demand

Citrini analyst Jukan stated that the HBM specifications for NVIDIA's Rubin Ultra may be reduced from 12 layers of HBM4E to 8 layers. Customers had requested a 4-layer product, but this was rejected by memory manufacturers, and the reduction may stop at 8 layers. The downgrade is primarily due to yield and cost pressures, as the cost of memory using 12 layers of HBM4E could account for about 70% of Rubin Ultra's overall material costs.

Software optimizations such as model quantization, MLA, and task splitting will transfer low-frequency accessed KV caches and model states to LPDDR, CXL, and NAND, while HBM will mainly retain the working set required for current computations. Customers' emphasis on HBM bandwidth has begun to surpass that on capacity.

Reducing the number of stacking layers can improve packaging yield and increase the shipment volume of HBM and AI accelerators, potentially expanding the total demand for HBM. Higher bandwidth requirements will also reduce the proportion of chips categorized by speed within the wafer, further consuming DRAM wafer production capacity. In the long term, HBM will eventually be replaced by new architectures, and the next two years will be a critical phase for memory manufacturers to expand into the logic domain.